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simplified application diagram 33984 v dd v dd mcu v dd v pwr i/o fs i/o so sclk si cs i/o i/o in0 i/o in1 a/d csns fsi hs0 gnd gnd gnd v dd v pwr pwrgnd wake si sclk so rst cs load hs1 load motorola semiconductor technical data this document contains informat ion on a product under development. motorola reserves the right to change or discontinue this product without notice. ? motorola, inc. 2004 document order number: MC33984/d rev 3.0, 03/2004 33984 preliminary information dual intelligent high-current self-protected silicon high-side switch (4.0 m ?) the 33984 is a dual self-protected 4.0 m ? silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33984 is designed for har sh environments, and it includes self-recovery features. the device is suit able for loads with high inrush current, as well as motors and all types of resistive and inductive loads. programming, control, and diagnostics are implemented via the serial peripheral interface (spi). a dedicated parallel input is available for alternate and pulse width modulation (pwm) control of each output. spi- programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. the 33984 is packaged in a power-enhanced 12 x 12 pqfn package with exposed tabs. features ?dual 4.0m ? max high-side switch with parallel input or spi control ? 6.0 v to 27 v operating voltage with standby currents < 5.0 a ? output current monitoring output with two spi-selectable current ratios ? spi control of overcurrent limit, overcurrent fault blanking time, output-off open load detection, output on/off control, watchdog timeout, slew rates, and fault status reporting ? spi status reporting of overcurrent, open and shorted loads, overtemperature, undervoltage and overvoltage shutdown, fail-safe pin status, and program status. ? enhanced 16 v reverse polarity v pwr protection dual high-side switch 4.0 m ? ordering information device temperature range (t a ) package pc33984pna/r2 -40 c to 125 c 16 pqfn scale 1:1 pna suffix case 1402-02 16-terminal pqfn 33984 simplified application diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 2 figure 1. 33984 simplifi ed internal block diagram gnd programmable watchdog 310ms?2500 ms overtemperature detection selectable output current recopy 1/20500 or 1/41000 open load detection logic spi 3.0 mhz selectable current detection time 0.15 ms?155 ms selectable over- 7.5a?25a selectable over- 100 a or 75 a internal regulator configurable switch delay 0 ms ?525 ms selectable slew rate gate drive overvoltage protection hs0 csns v pwr v dd cs sclk so si rst wake in0 fs fsi in1 hs1 hs0 hs1 current detection high current detection low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 3 csns in0 fs fsi cs sclk rst wake si v dd so in1 1 11 10 9 8 7 6 5 4 3 2 hs0 hs1 16 15 v pwr transparent top view of package 14 gnd 13 12 terminal functio n description terminal terminal name formal name definition 1 csns output current monitoring this term inal is used to output a current propor tional to the designated hs0-1 output. that current is fed into a ground-referenced resistor and its voltage is monitored by an mcu's a/d. the channel to be monitored is selected via the spi. this terminal can be tri-stated through spi. 2 wake wake this terminal is used to input a logi c [1] signal so as to enable the watchdog timer function. an internal clamp protects this terminal from high damaging voltages when the output is current limited with an external resi stor. this input has an internal passive pull- down. 3 rst reset (active low) this input terminal is used to initia lize the device configurati on and fault registers, as well as place the device in a low current sleep mode. the terminal also starts the watchdog timer when transitioning from logic low to logic high. th is terminal should not be allowed to be logic high until v dd is in regulation. this terminal has an internal passive pull-down. 4 in0 serial input this input terminal is used to directly control the output hs0. this input has an internal active pull-down and requires cmos logic leve ls. this input may be configured via spi. 5 fs fault status (active low) this is an open drain configured output requiring an external pull-up resistor to v dd for fault reporting. when a device fault condition is detected, this terminal is active low. specific device diagnostic faults are reported via the spi so terminal. 6 fsi fail-safe input the value of the resistance c onnected between this terminal and ground determines the state of the outputs after a watchdog timeout occurs. depending on the resistance value, either all outputs are off, on, or the output hso only is on. when the fsi terminal is connected to g nd, the watchdog circuit and fail -safe operation are disabled. this terminal incorporates an active internal pull-up. 7 cs chip select (active low) this input te rminal is connected to a chip select output of a master microcontroller (mcu). the mcu determines which device is addressed (selected) to receive data by pulling the cs terminal of the selected device logic low, enabling spi communication with the device. other unselected devices on the serial link having their cs terminals pulled-up logic high disregard the spi communication data sent. 8 sclk serial clock this input terminal is connected to the mcu providing the required bit shift clock for spi communication. it transitions one time per bit transferred at an operating frequency, f spi , defined by the communication interface. the 50 percent duty cycle cmos-level serial clock signal is idle between command transfers. the signal is used to shift data into and out of the device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 4 9 si serial input this is a command data input terminal connected to the spi serial data output of the mcu or to the so terminal of the previous device of a daisy chain of devices. the input requires cmos logic-level signals and inco rporates an internal active pull-down. device control is facilitated by the input's re ceiving the msb first of a serial 8-bit control command. the mcu ensures data is availabl e upon the falling edge of sclk. the logic state of si present upon the rising edge of sclk loads that bit command into the internal command shift register. 10 v dd digital drain voltage (power) this is an external voltage input terminal used to supply power to the spi circuit. in the event v dd is lost, an internal supply provides po wer to a portion of the logic, ensuring limited functionality of the device. 11 so serial output this is an output terminal connected to the spi serial data input terminal of the mcu or to the si terminal of the next device of a daisy chain of devices. this output will remain tri-stated (high impedance off condition) so long as the cs terminal of the device is logic high. so is only active when the cs terminal of the device is asserted logic low. the generated so output signals ar e cmos logic levels. so output data is available on the falling edge of sclk and tr ansitions immediatel y on the rising edge of sclk. 12 in1 serial input this input terminal is used to directly control the output hs1. this input has an internal active pull-down and requires cmos logic leve ls. this input may be configured via spi. 13 gnd ground this terminal is the ground for the logic and analog circuitry of the device. 14 v pwr positive power supply this terminal connects to the positive power supply and is the source input of operational power for the device. the v pwr terminal is a backs ide surface mount tab of the package. 15 hs1 high-side output 1 protected 4.0 m ? high-side power output to the load. 16 hs0 high-side output 0 protected 4.0 m ? high-side power output to the load. terminal function d escription (continued) terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 5 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit operating voltage range steady-state v pwr -16 to 41 v v dd supply voltage v dd 0 to 5.5 v input/output voltage (note 1) v in[0:1] , rst , fsi csns, si, sclk, cs , fs -0.3 to 7.0 v so output voltage (note 1) v so -0.3 to v dd +0.3 v wake input clamp current i cl(wake) 2.5 ma csns input clamp current i cl(csns) 10 ma output current (note 2) i hs[0:1] 30 a output clamp energy (note 3) e cl[0:1] 0.75 j storage temperature t stg -55 to 150 c operating junction temperature t j -40 to 150 c thermal resistance (note 4) junction to case junction to ambient r jc r ja <1.0 20 c/w esd voltage human body model (note 5) machine model (note 6) v esd1 v esd2 2000 200 v terminal soldering temperature (note 7) t solder 240 c notes 1. exceeding voltage limits on rst , in[0:1], or fsi terminals may cause a malfunction or permanent damage to the device. 2. continuous high-side output current rati ng so long as maximum junction temperature is not exceeded. calculation of maximum ou tput current using package thermal resistance is required. 3. active clamp energy using single-pulse method (l = 16 mh, r l = 0, v pwr = 12 v, t j = 150c). 4. device mounted on a 2s2p test board according to jedec jesd51-2. 5. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ?). 6. esd2 testing is performed in ac cordance with the machine model (c zap = 200 pf, r zap = 0 ?). 7. terminal soldering temperature limit is for 10 seconds maximum duration. not desi gned for immersion sol dering. exceeding thes e limits may cause malfunction or permanent damage to the device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 6 static electrical characteristics characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input battery supply voltage range full operational v pwr 6.0 ? 27 v v pwr operating supply current output on, i hs0 and i hs1 = 0 a i pwr(on) ??20 ma v pwr supply current output off, open load detection disabled, wake > 0.7 v dd , rst = v logic high i pwr(sby) ??5.0 ma sleep state supply current (v pwr < 14 v, rst < 0.5 v, wake < 0.5 v) t j = 25 c t j = 85 c i pwr(sleep) ? ? ? ? 10 50 a v dd supply voltage v dd(on) 4.5 5.0 5.5 v v dd supply current no spi communication 3.0 mhz spi communication i dd(on) ? ? ? ? 1.0 5.0 ma v dd sleep state current i dd(sleep) ??5.0 a overvoltage shutdown v pwr(on) 28 32 36 v overvoltage shutdown hysteresis v pwr(ovhys) 0.2 0.8 1.5 v undervoltage output shutdown (note 8) v pwr(uv) 5.0 5.5 6.0 v undervoltage hysteresis (note 9) v pwr(uvhys) ?0.25?v undervoltage power-on reset v pwr(uvpor) ??5.0v notes 8. output will automatically recover to instructed state when v pwr voltage is restored to normal so long as the v pwr degradation level did not go below the undervoltage power-on reset threshold. this applie s to all internal device l ogic that is supplied by v pwr and assumes that the external v dd supply is within specification. 9. this applies when the undervoltage fault is not latched (in = 0). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 7 static electrical charac teristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output output drain-to-source on resistance ( i hs[0:1] = 30 a, t j = 25 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on)25 ? ? ? ? ? ? 6.0 4.0 4.0 m ? output drain-to-source on resistance (i hs[0:1] = 30 a, t j = 150 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on)150 ? ? ? ? ? ? 10.2 6.8 6.8 m ? output source-to-drain on resistance i hs[0:1] = 15 a, t j = 25 c (note 10) v pwr = -12 v r ds(on) ??8.0 m ? output overcurrent high detection levels (9.0 v < v pwr < 16 v) soch = 0 soch = 1 i och0 i och1 80 60 100 75 120 90 a overcurrent low detection levels (socl[2:0]) 000 001 010 011 100 101 110 111 i ocl0 i ocl1 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 21 18 16 14 12 10 8.0 6.0 25 22.5 20 17.5 15 12.5 10 7.5 29 27 24 21 17 15 12 9.0 a current sense ratio (9.0 v < v pwr < 16 v, csns < 4.5 v) dicr d2 = 0 dicr d2 = 1 c sr0 c sr1 ? ? 1/20500 1/41000 ? ? current sense ratio (c sr0 ) accuracy output current 5.0 a 10 a 12.5 a 15 a 20 a 25 a c sr0_acc -20 -14 -13 -12 -13 -13 ? ? ? ? ? ? 20 14 13 12 13 13 % notes 10. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 8 static electrical charac teristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output (continued) current sense ratio (c sr1 ) accuracy output current 5.0 a 10 a 12.5 a 15 a 20 a 25 a c sr1_acc -25 -19 -18 -17 -18 -18 ? ? ? ? ? ? 25 19 18 17 18 18 % maximum current sense clamp voltage i csns = 15 ma v cl(maxcsns) 4.5 6.0 7.0 v open load detection current (note 11) i oldc 30 ? 100 a output fault detection threshold output programmed off v old(thres) 2.0 3.0 4.0 v output negative clamp voltage 0.5 a < = i hs[0:1] < = 2.0 a, output off v cl -20 ? ? v overtemperature shutdown (note 12) t a = 125 c, output off t sd 150 175 190 c overtemperature shutdown hysteresis (note 12) t sd(hys) 5.0 ? 20 c notes 11. output off open load detection current is the current required to flow through the load for the purpose of detecting the exi stence of an open load condition when the specific output is commanded off. 12. guaranteed by process monitoring. not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 9 static electrical charact eristics (continued) characteristics noted under conditions 4.5 v v dd 5.5v, 6.0v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit control interface input logic high voltage (note 13) v ih 0.7v dd ? ? v input logic low voltage (note 13) v il ? ? 0.2v dd v input logic voltage hysteresis (note 14) v in[0:1](hys) 100 350 750 mv input logic pull-down current (sclk, in, si) i dwn 5.0 ? 20 a rst input voltage range v rst 4.5 5.0 5.5 v so, fs tri-state capacitance (note 15) c so ? ? 20 pf input logic pull-down resistor ( rst ) and wake r dwn 100 200 400 k ? input capacitance (note 15) c in ? 4.0 12 pf wake input clamp voltage (note 16) i cl(wake) <2.5ma v cl(wake) 7.0 ? 14 v wake input forward voltage i cl(wake) = -2.5 ma v f(wake) -2.0 ? -0.3 v so high-state output voltage i oh = 1.0 ma v soh 0.8v dd ? ? v fs , so low-state output voltage i ol = -1.6 ma v sol ? 0.2 0.4 v so tri-state leakage current cs > 0.7 v dd i so(leak) -5.0 0 5.0 a input logic pull-up current (note 17) cs , v in[0:1] > 0.7 v dd i up 5.0 ? 20 a fsi input pin external pull-down resistance fsi disabled, hs[0:1] indeterminate fsi enabled, hs[0:1] off fsi enabled, hs0 on, hs1 off fsi enabled, hs[0:1] on rfs rfsdis rfsoffoff rfsonoff rfsonon ? 6.0 15 30 0 6.5 17 ? 1.0 7.0 19 ? k ? notes 13. upper and lower logic threshold voltage range applies to si, cs , sclk, rst , in[0:1], and wake input signals. the wake and rst signals may be supplied by a derived voltage reference to v pwr . 14. parameter is guaranteed by processi ng monitoring but is not production tested. 15. input capacitance of si, cs , sclk, rst , and wake. this parameter is guaranteed by pr ocess monitoring but is not production tested. 16. the current must be limited by a series resistance when using voltages > 7.0 v. 17. pull-up current is with cs open. cs has an active internal pull-up to v dd . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 10 dynamic electrical characteristics characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output timing output rising slow slew rate a (dicr d3 = 0) (note 18) 9.0 v < v pwr < 16 v sr ra_slow 0.2 0.6 1.2 v/ s output rising slow slew rate b (dicr d3 = 0) (note 19) 9.0 v < v pwr < 16 v sr rb_slow 0.03 0.1 0.3 v/ s output rising fast slew rate a (dicr d3 = 1) (note 18) 9.0 v < v pwr < 16 v sr ra_fast 0.4 1.0 4.0 v/ s output rising fast slew rate b (dicr d3 = 1) (note 19) 9.0 v < v pwr < 16 v sr rb_fast 0.03 0.1 1.2 v/ s output falling slow slew rate a (dicr d3 = 0) (note 18) 9.0 v < v pwr < 16 v sr fa_slow 0.2 0.6 1.2 v/ s output falling slow slew rate b (dicr d3 = 0) (note 19) 9.0 v < v pwr < 16 v sr fb_slow 0.03 0.1 0.3 v/ s output falling fast slew rate a (dicr d3 = 1) (note 18) 9.0 v < v pwr < 16 v sr fa_fast 0.8 2.0 4.0 v/ s output falling fast slew rate b (dicr d3 = 1) (note 19) 9.0 v < v pwr < 16 v sr fb_fast 0.1 0.35 1.2 v/ s output turn-on delay time in fast/slow slew rate (note 20) dicr = 0, dicr = 1 t dly(on) 1.0 15 100 s output turn-off delay time in slow slew rate mode (note 21) dicr = 0 t dly_slow(off) 20 230 500 s output turn-off delay time in fast slew rate mode (note 21) dicr = 1 t dly_fast(off) 10 60 200 s direct input switching frequency (dicr d3 = 0) f pwm ? 300 ? hz notes 18. rise and fall slew rates a measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr -3.5 v. these parameters are guaranteed by process monitoring. 19. rise and fall slew rates b measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr -3.5 v. these parameters are guaranteed by process monitoring. 20. turn-on delay time measured from rising edge of in [0:1] signal that would turn the output on to v hs[0:1] = 0.5 v with r l = 5.0 ? resistive load. 21. turn-off delay time measured from falling edge that would turn the output off to v hs[0:1] = v pwr -0.5 v with r l =5.0 ? resistive load. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 11 power output timing (continued) overcurrent detection blanking time (oclt[1:0]) 00 01 10 11 t ocl0 t ocl1 t ocl2 t ocl3 108 7.0 0.8 0.08 155 10 1.2 0.15 202 13 1.6 0.25 ms overcurrent high detection blanking time t och 1.0 10 20 s cs to csns valid time (note 22) cns val ? ? 10 s hs0 switching delay time (osd[2:0]) 000 001 010 011 100 101 110 111 t osd0 t osd1 t osd2 t osd3 t osd4 t osd5 t osd6 t osd7 ? 55 110 165 220 275 330 385 0 75 150 225 300 375 450 525 ? 95 190 285 380 475 570 665 ms hs1 switching delay time (osd[2:0]) 000 001 010 011 100 101 110 111 t osd0 t osd1 t osd2 t osd3 t osd4 t osd5 t osd6 t osd7 ? ? 110 110 220 220 330 330 0 0 150 150 300 300 450 450 ? ? 190 190 380 380 570 570 ms watchdog timeout (wd[1:0]) (note 23) 00 01 10 11 t wdto0 t wdto1 t wdto2 t wdto3 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms notes 22. time necessary for the csns to be within 5% of the targeted value. 23. watchdog timeout delay measured from the rising edge of wake to rst from a sleep state condition to output turn-on with the output driven off and fsi floating. the values shown are for wdr setting of [00]. the accuracy of t wdto is consistent for all configured watchdog timeouts. dynamic electrical char acteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 12 dynamic electrical cha racteristics (continued) characteristics noted un der conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit spi interface characteristics recommended frequency of spi operation f spi ? ? 3.0 mhz required low state duration for rst (note 24) t wrst ? 50 350 ns rising edge of cs to falling edge of cs (required setup time) (note 25) t cs ? ? 300 ns rising edge of rst to falling edge of cs (required setup time) (note 25) t enbl ? ? 5.0 s falling edge of cs to rising edge of sclk (required setup time) (note 25) t lead ? 50 167 ns required high state duration of sclk (required setup time) (note 25) t wsclkh ? ? 167 ns required low state duration of sclk (required setup time) (note 25) t wsclkl ? ? 167 ns falling edge of sclk to rising edge of cs (required setup time) (note 25) t lag ? 50 167 ns si to falling edge of sclk (required setup time) (note 26) t si(su) ? 25 83 ns falling edge of sclk to si (required setup time) (note 26) t si(hold) ? 25 83 ns so rise time c l = 200 pf t rso ? 25 50 ns so fall time c l = 200 pf t fso ? 25 50 ns si, cs , sclk, incoming signal rise time (note 26) t rsi ? ? 50 ns si, cs , sclk, incoming signal fall time (note 26) t rsi ? ? 50 ns time from falling edge of cs to so low impedance (note 27) t so(en) ? ? 145 ns time from rising edge of cs to so high impedance (note 28) t so(dis) ? 65 145 ns time from rising edge of sclk to so data valid (note 29) 0.2 v dd so 0.8 v dd , c l = 200 pf t valid ? 65 105 ns notes 24. rst low duration measured with outputs enabled and going to off or disabled condition. 25. maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller. 26. rise and fall time of incoming si, cs , and sclk signals suggested for desi gn consideration to prevent the occurrence of double pulsing. 27. time required for output status data to be available for use at so. 1.0 k ? on pull-up on cs . 28. time required for output status data to be terminated at so. 1.0 k ? on pull-up on cs . 29. time required to obtain valid data out from so following the rise of sclk. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 13 timing diagrams figure 2. output slew rate and time delays figure 3. overcurrent shutdown figure 4. overcurrent low and high detection vpwr vpwr - 0.5v vpwr - 3v 0.5v tdly ( off) srra srrb srfa srfb cs tdly (on) v pwr v pwr -0.5 v v pwr -3.5 v 0.5 v t dly(on) t dly(off) sr rb sr fb sr fa sr ra i oclx i ochx i load1 i load1 t oclx t och time load current i och0 t ocl0 t ocl1 t ocl2 t ocl3 t ochx time load current i och1 i ocl0 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 i ocl1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 14 figure 5. input timing switching characteristics figure 6. sclk waveform and valid so data delay time si rstb csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rst sclk si cs 0.2 v dd t wrst t enbl 0.7 v dd t lead t wsclkh t rsi 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd t si(su) t wsclkl t si(hold) t fsi 0.7 v dd t cs t lag v ih v ih v il v il v ih v il v ih v ih so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 0.7 v dd sclk so so v oh v ol v oh v ol v oh v ol 1.0 v 0.2 v dd 0.7 v dd t rso t fso 0.2 v dd t so(en) t so(dis) 3.5 v low to high high to low t valid f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 15 system/application information introduction the 33984 is a dual self-protected 4.0 m ? silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33984 is designed for harsh environments, and it includes self-recovery features. the device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. programming, control, and diagnostics are implemented via the serial peripheral interface (spi). a dedicated parallel input is available for alternate a nd pulse width modulation (pwm) control of each output. spi-progr ammable fault trip thresholds allow the device to be adjusted for optimal performance in the application. the 33984 is packaged in a power-enhanced 12 x 12 pqfn package with exposed tabs. functional description spi protocol description the spi interface has a full duplex, three-wire synchronous data transfer with four i/o lines associated with it: serial clock (sclk), serial input (si), serial output (so), and chip select ( cs ). the si/so terminals of the 33984 follow a first-in first-out (d7/d0) protocol with both input and output words transferring the most significant bit (msb) fi rst. all inputs are compatible with 5.0 v cmos logic levels. the spi lines perform the following functions: serial clock (sclk) serial clocks (sclk) the inter nal shift regist ers of the 33984 device. the serial input (si) term inal accepts data into the input shift register on the falling edge of the sclk signal while the serial output (so) terminal shif ts data information out of the so line driver on the rising edge of the sclk signal. it is important that the sclk terminal be in a logic low state whenever cs makes any transition. for this reason, it is recommended that the sclk terminal be in a logic [0] state whenever the device is not accessed ( cs logic [1] state). sclk has an internal pull- down, i dwn . when cs is logic [1], signals at the sclk and si terminals are ignored and so is tri-stated (high impedance). (see figure 7 and figure 8 on page 16.) serial input (si) this is a serial interface (si) command data inpu t terminal. si instruction is read on the falling edge of sclk. an 8-bit stream of serial data is required on the si terminal, starting with d7 to d0. the internal registers of the 33984 are configured and controlled using a 4-bit addressing scheme, as shown in table 1 , page 16. register addressing and configuration are described in table 2 , page 17. the si input has an internal pull- down, i dwn . serial output (so) the so data terminal is a tri-stateable output from the shift register. the so terminal remains in a high impedance state until the cs terminal is put into a logic [0] state. the so data is capable of reporting the stat us of the output, the device configuration, and the state of the key inputs. the so terminal changes states on the rising edge of sclk and reads out on the falling edge of sclk. fault and input status descriptions are provided in table 11 , page 21. chip select (cs ) the cs terminal enables communication with the master microcontroller (mcu). when this te rminal is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the mcu. the 33984 device latches in data from the input shift registers to t he addressed registers on the rising edge of cs . the device transfers status information from the power output to the shift register on the falling edge of cs . the so output driver is enabled when cs is logic [0]. cs should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. cs has an internal pull-up, i up . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 16 figure 7. single 8-bit word spi communication figure 8. multiple 8-bit word spi communication serial input communication spi communication is accomplished using 8-bit messages. a message is transmitted by the mcu starting with the msb, d7, and ending with the lsb, d0 ( table 1 ). each incoming command message on the si terminal can be interpreted using the following bit assignments: the msb (d7) is the watchdog bit and in some cases a register address bit common to both outputs or specific to an output; the next three bits, d6?d4, are used to select the command re gister; and the remaining four bits, d3?d0, are used to confi gure and control the outputs and their protection features. multiple messages can be tr ansmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm trans mitted data, as long as the messages are all multiples of ei ght bits. any attempt made to latch in a message that is not eight bits will be ignored. the 33984 has defined register s, which are used to configure the device and to co ntrol the state of the output. table 2 page 17, summarizes the si registers. the registers are addressed via d6?d4 of the incoming spi word ( table 1 ). csb si sclk d7 d1 d2 d3 d4 d5 d6 d0 od7 od6 od1 od2 od3 od4 od5 notes: od0 so 1. rstb is in a logic 1 state during the above operation. 2. d0, d1, d2, ..., and d7 relate to the most recent ordered entry of data into the spss 3. od0, od1, od2, ..., and od7 relate to the first 8 bits of ordered fault and status data out of the device. cs so rst 1. rst is a logic [1] state during the above operation. 2. d7?d0 relate to the most recent ordered entry of data into the device. 3. od7?od0 relate to the first 8 bits of ordered fault and status data out of the device. notes csb si sclk d7 d1* d2* d5* d6* d7* d0 d1 d6 d5 d2 d0* od5 od6 od7 d6 d7 od0 od1 od2 d1 d2 d5 f ig u r e 4 b . m u l t ip l e 8 b it w o r d s p i c o m m u n ic a t io n notes : d0 so 1. r s tb is in a logic 1 state during the above operation. 2 . d 0 , d 1 , d 2 , ..., a n d d 7 re la te to th e m o s t re c e n t o rd e re d e n try o f d a ta in to th e s p s s 3. o d 0, o d 1, o d 2, ..., and o d 7 relate to the first 8 bits of ordered fault and status data out of the device. 4. o d 0, o d 1, o d 2, ..., and o d 7 represent the first 8 bits of ordered fault and status data out of the s pss cs sclk si so rst 1. rst is a logic [1] state during the above operation. 2. d7?d0 relate to the most recent ordered entry of data into the device. 4. od7?od0 relate to the first 8 bits of or dered fault and status data out of the device. notes 3. d7*?d0* relate to the previous 8 bits (last command wo rd) of data that was previously shifted into the device. table 1. si message bit assignment bit sig si msg bit message bit description msb d7 register address bit for output selection. also used for watchdog: toggled to satisfy watchdog requirements. d6?d4 register address bits. d3?d1 used to configure the inputs, outputs, and the device protection features and so status content. lsb d0 used to configure the inputs, outputs, and the device protection features and so status content. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 17 device register addressing the following section describes the possible register addresses and their impact on device operation. address x000?status register (statr) the start register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. the register bits d2, d1, d0 determine the content of th e first eight bits of so data. when the register content is spec ific to one of the two outputs, the bit d7 is used to select the desired output. in addition to the device status, this feature prov ides the ability to read the content of the o cr, sochlr, cdtolr, dicr, osdr, wdr , nar, and uovr registers. (refer to the section entitled serial output c ommunication ( device status return data) beginning on page 19.) address x001?output control register (ocr) the ocr register allows the mcu to control the outputs through the spi. incoming message bit d0 reflects the desired states of the high-side output hs0 (in_spi): a logic [1] enables the output switch and a logic [0] turns it off. a logic [1] on message bit d1 enables the current sense (csns) terminal. similarly, incoming message bit d2 reflects the desired states of the high-side output hs1 (in_ spi). a logic [1] enables the output switch and a logic [0] turns it off. a logic [1] on message bit d3 enables the csns terminal. in the event that the current sense is enabled for bo th outputs, the current will be summed. bit d7 is used to feed the watchdog if enabled. address x010? select overcurrent high and low register (sochlr) the sochlr register allows the mcu to configure the output overcurrent low and high detection levels, respectively. each output is independently selected for configuration based on the state of the d7 bit; a writ e to this register when d7 is logic [0] will configure the current detect levels for the hs0. similarly, if d7 is logic [1] when this register is written, hs1 is configured. each output can be c onfigured to different levels. in addition to protecting the device, this slow blow fuse emulation feature can be used to optimize th e load requirements matching system characteristics. bits d2?d0 set the overcurrent low detection level to one of eight possible levels, as shown in table 3 . bit d3 sets the overcurrent high detection level to one of two levels, which is described in table 4 . address x011?current detection time and open load register (cdtolr) the cdtolr register is used by the mcu to determine the amount of time the device will allow an overcurrent low condition before output latches off occurs. each output is independently selected for configur ation based on the state of the d7 bit. a write to this register when bit 7 is logic [0] will configure the timeout fo r the hs0. similarly, if d7 is logic [1] when this register is written, then hs1 is configured. bits d1? d0 allow the mcu to select one of four fault blanking times defined in table 5 , page 18. note that these timeouts apply only to the overcurrent low detection levels. if the selected overcurrent high level is reached, the device will latch off within 20 s. table 2. serial input address and configuration bit map si register serial input data d7 d6 d5 d4 d3 d2 d1 d0 statr so a3 0 0 0 0 soa2 soa1 soa0 ocr x 0 0 1 csns1 en in1_spi csns0 en in0_spi sochlr s 0 1 0 sochs socl2s socl1s socl0s cdtolr s 0 1 1 ol dis s cd dis s oclt1s oclt0s dicr s 1 0 0 fast srs csns highs in dis s a/os osdr 0 1 0 1 0 osd2 osd1 osd0 wdr 1 1 0 1 0 0 wd1 wd0 nar 0 1 1 0 0 0 0 0 uovr 1 1 1 0 0 0 uv_dis ov_dis test x 1 1 1 motorola internal use (test) x = don?t care. s = selection of output: logic [0] = hs0, logic [1] = hs1. table 3. overcurrent low detection levels socl2 (d2) socl1 (d1) socl0 (d0) overcurrent low detection (amperes) 0 0 0 25 0 0 1 22.5 0 1 0 20 0 1 1 17.5 1 0 0 15 1 0 1 12.5 1 1 0 10 1 1 1 7.5 table 4. overcurrent high detection levels soch (d3) overcurrent high detection (amperes) 0 100 1 75 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 18 a logic [1] on bit d2 disables the overcurrent low (cd dis) detection timeout feature. a logic [1] on bit d3 disables the open load (ol) detection feature. address x100?direct input control register (dicr) the dicr register is used by th e mcu to enable, disable, or configure the direct in terminal control of each output. each output is independently selected fo r configuration based on the state of bit d7. a write to this register when bit d7 is logic [0] will configure the direct input control fo r the hs0. similarly, if d7 is logic [1] when this register is written, then hs1 is configured. a logic [0] on bit d1 will enable the output for direct control by the in terminal. a logic [1] on bit d1 will disable the output from direct control. while addressing th is register, if the input was enabled for direct control, a logic [1] for the d0 bit will result in a boolean and of the in terminal with its corresponding d0 message bit when addressing the ocr register. similarly, a logic [0] on the d0 terminal results in a boolean or of the in terminal with the corresponding message bits when addressing the ocr register. the dicr register is useful if there is a need to independently turn on and off several loads that are pwm?d at the same frequency and duty cycle with only one pwm signal. this type of operation can be accomplished by connecting the pertinent direct in terminals of several devices to a pwm output port from the mcu and configuring each of the outputs to be controlled via their respective direct in terminal. the dicr is then used to boolean and the di rect in(s) of each of the outputs with the dedicated spi bit that also controls the output. each configured spi bit can now be used to enable and disable the common pwm signal from controlling its assigned output. a logic [1] on bit d2 is used to select the high ratio (c sr1 , 1/41000) on the csns terminal for the selected output. the default value [0] is used to select the low ratio (c sr0 , 1/20500). a logic [1] on bit d3 is used to select the high speed slew rate for the selected output. the def ault value [0] corresponds to the low speed slew rate. address 0101?output switchin g delay register (osdr) the osdr register config ures the device with a programmable time delay that is active during output on transitions initiated via spi (not via direct input). a write to this register config ures both outputs for different delay. whenever the input is commanded to transition from [0] to [1], both outputs will be held off for the time delay configured in the osdr. the prog ramming of the contents of this register have no effect on device fail-safe mode operation. the default value of the osdr regi ster is 000, equating to no delay. this feature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be switched on with a single command. there are eight selectable output switching delay times that range from 0 ms to 525 ms (refer to table 6 ). address 1101?watchdog register (wdr) the wdr register is used by the mcu to configure the watchdog timeout. watchdog timeout is configured using bits d1 and d0. when d1 and d0 bits are programmed for the desired watchdog timeout period, the wd bit (d7) should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence (refer to table 7 ). address 0110?no action register (nar) the nar register can be used to no-operation fill spi data packets in a daisy chain spi configuration. this allows devices to not be affected by commands being clocked over a daisy- chained spi configuration, and by toggling the wd bit (d7) the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device. table 5. overcurrent low detection blanking timing oclt[1:0] timing 00 155 ms 01 10 ms 10 1.2 ms 11 150 s table 6. switching delay osd[2:0] (d2, d1, d0) turn on delay (ms) hs0 turn on delay (ms) hs1 000 0 0 001 75 0 010 150 150 011 225 150 100 300 300 101 375 300 110 450 450 111 525 450 table 7. watchdog timeout wd[1:0] (d1, d0) timing (ms) 00 620 01 310 10 2500 11 1250 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 19 address 1110?undervoltage/overvoltage register (uovr) the uovr register can be used to disable or enable the overvoltage and/or undervoltage pr otection. by default ([0]), both protections are active. wh en disabled, an undervoltage or overvoltage condition fault will not be reported in the output fault register. address x111?test the test register is reserved for test and is not accessible with spi during normal operation. serial output communication (device status return data) when the cs terminal is pulled low, t he output status register is loaded. meanwhile, the data is clocked out msb- (od7-) first as the new message data is clocked into the si terminal. the first eight bits of data clocking out of the so, and following a cs transition, are dependant upon the previously written spi word. any bits clocked out of the so terminal after the first eight will be representative of the initial me ssage bits clocked into the si terminal since the cs terminal first transitioned to a logic [0]. this feature is useful for daisy chaining devices as well as message verification. a valid message length is determined following a cs transition of [0] to [1]. if there is a valid message length, the data is latched into the appropriate registers. a valid message length is a multiple of eight bits. at th is time, the so terminal is tri- stated and the fault status register is now able to accept new fault status information. the output status register correct ly reflects the status of the statr-selected register data at the time that the cs is pulled to a logic [0] during spi communication and/or for the period of time since the last valid spi communication, with the following exceptions: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ? battery transients below 6. 0 v resulting in an under- voltage shutdown of the outputs may result in incorrect data loaded into the status register. the so data transmitted to the mcu during the first spi communication following an undervoltage v pwr condition should be ignored. ? the rst terminal transition from a logic [0] to [1] while the wake terminal is at logic [0] may result in incorrect data loaded into the status register . the so data transmitted to the mcu during the first spi communication following this condition should be ignored. serial output bit assignment the 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. table 8 summarizes the so register content. bit od7 reflects the state of the watchdog bit (d7) addressed during the prior communication. the value of the previous d7 will determine which output the st atus information applies to for the fault (fltr), sochlr, cdtolr, and dicr registers. so data will represent information ranging from fault status to register contents, user selected by writing to the statr bits d2, d1, and d0. note that the so data will continue to reflect the information for each output (depending on the previous d7 state) that was selected during the most recent statr write until changed with an updated statr write. table 8. serial output bit map description previous statr d7, d2, d1, d0 serial output returned data soa3 soa2 soa1 soa0 od7 od6 od5 od4 od3 od2 od1 od0 s 0 0 0 s otfs ochfs oclfs olfs uvf ovf faults x 0 0 1 x 0 0 1 csns1 en in1_spi csns0 en in0_spi s 0 1 0 s 0 1 0 sochs socl2s socl1s socl0s s 0 1 1 s 0 1 1 ol dis s cd dis s oclt1s oclt0s s 1 0 0 s 1 0 0 fast srs csns high s in dis s a/os 0 1 0 1 0 1 0 1 fsm_hs0 osd2 osd1 osd0 1 1 0 1 1 1 0 1 fsm_hs1 wdto wd1 wd0 0 1 1 0 0 1 1 0 in1 terminal in0 terminal fsi terminal wake terminal 1 1 1 0 1 1 1 0 ? ? uv_dis ov_dis x 1 1 1 ? ? ? ? ? ? ? ? s = selection of output: logic [0] = hs0, logic [1] = hs1. x = don?t care. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 20 previous address soa[2:0]=000 if the previous three msbs are 000, bits od6?od0 will reflect the current state of the fault register (fltr) corresponding to the output previously selected with the bit od7 ( table 9 ). previous address soa[2:0]=001 data in bits od1 and od0 contain csns0 en and in0_spi programmed bits, respectively. data in bits od3 and od2 contain csns0 en and in0_spi programmed bits, respectively. previous address soa[2:0]=010 the data in bit od3 contain the programmed overcurrent high detection level (refer to table 4 , page 17), and the data in bits od2, od1, and od0 contai n the programmed overcurrent low detection levels (refer to table 3 , page 17). previous address soa[2:0]=011 data returned in bits od1 and od0 are current values for the overcurrent dead time, illustrated in table 5 , page 18. bit od2 reports if the overcurrent detect ion timeout feature is active. od3 reports if the open load circuitry is active. previous address soa[2:0]=100 the returned data contain the programmed values in the dicr. previous address soa[2:0]=101 ? soa3 = 0. the returned data contain the programmed values in the osdr. bit od3 (fsm_hs0) reflects the state of the output hs0 in the fail-safe mode after a watchdog timeout occurs. ? soa3 = 1. the returned data contain the programmed values in the wdr. bit od2 (wdto) reflects the status of the watchdog circuitry. if wd to bit is [1], the watchdog has timed out and the device is in fail-safe mode. if wdto is [0], the device is in normal mode (assuming the device is powered and not in sleep mode), with the watchdog either enabled or disabled. bit od3 (fsm_hs1) reflects the state of the output hs1 in the fail-safe mode after a watchdog timeout occurs. previous address soa[2:0] =110 ? soa3 = 0. od3 to od0 return the state of the in1, in0, fsi, and wake terminal, respectively ( table 10 ). ? soa3 = 1. the returned data contain the programmed values in the uovr. bit od1 reflects the state of the undervoltage protection and bit od0 reflects the state of the overvoltage protection (refer to table 8 , page 19). previous address soa[2:0]=111 null data. no previous register read back command received, so bits od2, od1, and od0 are null, or 000. table 9. fault register od7 od6 od5 od4 od3 od2 od1 od0 s otf ochfs oclfs olfs uvf ovf faults od7 (s) = selection of output: logic [0] = hs0, logic [1] = hs1. od6 (otf) = overtemperature flag. od5 (ochfs) = overcurrent high flag. (this fault is latched.) od4 (oclfs) = overcurrent low flag. (this fault is latched.) od3 (olfs) = open load flag. od2 (uvf) = undervoltage flag. (thi s fault is latched or not latched.) od1 (ovf) = overvoltage flag. od0 (faults) = this flag reports a fault and is reset by a read operation. note the fs terminal reports a fault. for latched faults, this terminal is reset by a new switch on command (via spi or direct input in). table 10. terminal register od3 od2 od1 od0 in1 terminal in0 terminal fsi terminal wake terminal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 21 modes of operation the 33984 has four operating modes: sleep, normal, fail- safe, and fault. refer to table 11 for details. sleep mode the default mode of the 33984 is the sleep mode. this is the state of the device after first applying battery voltage (v pwr ), prior to any i/o transitions. this is also the state of the device when the wake and rst are both logic [0]. in the sleep mode, the output and all unused internal circuitry, such as the internal 5.0 v regulator, are off to minimize current draw. in addition, all spi-configurable features of the device are as if set to logic [0]. the device will transition to the normal or fail-safe operating modes based on the wake and rst inputs as defined in table 11 . normal mode the 33984 is in normal mode when: ?v pwr is within the normal voltage range. ? rst terminal is logic [1]. ? no fault has occurred. fail-safe mode fail-safe mode and watchdog if the fsi input is not grounded, the watchdog timeout detection is active w hen either the wake or rst input terminal transitions from logic [0] to [1 ]. the wake input is capable of being pulled up to v pwr with a series of limiting resistance that limits the internal clamp current according to the specification. the watchdog timeout is a multiple of an internal oscillator and is specified in table 7 , page 18 . as long as the wd bit (d7) of an incoming spi message is toggled within the minimum watchdog timeout period (wdto), based on the programmed value of the wdr the device will o perate normally. if an internal watchdog timeout occurs before the wd bit, the device will revert to a fail-safe mode until the device is reinitialized. during the fail-safe mode, the outputs will be on or off depending upon the resistor rfs c onnected to the fsi terminal, regardless of the state of the va rious direct inputs and modes ( table 12 ). in this mode, the spi re gister content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (socl, soch, and oclt). then the watchdog, overvo ltage, overtemperature, and overcurrent circuitry (with defaul t value) are fully operational. the fail-safe mode can be detected by monitoring the wdto bit d2 of the wd register. this bit is logic [1] when the device is in fail-safe mode. th e device can be brought out of the fail-safe mode by transitioning the wake and rst terminals from logic [1] to logic [0] or forcing the fsi terminal to logic [0]. table 11 summarizes the various methods for resetting the device from the latched fail-safe mode. if the fsi terminal is tied to gnd, the watchdog fail-safe operation is disabled. loss of v dd if the external 5.0 v supply is no t within specification, or even disconnected, all register content is reset. the two outputs can still be driven by the direct i nputs in[1:0]. the 33984 uses the battery input to power the output mosfet-related current sense circuitry and any other internal logic providing fail-safe device operation with no v dd supplied. in this state, the watchdog, overvoltage, overte mperature, and overcurrent circuitry are fully operational with default values. table 11. fail-safe operation and transitions to other 33984 modes mode fs wake rst wdto comments sleep x 0 0 x device is in sleep mode. all outputs are off. normal 1 x 1 no normal mode. watchdog is active if enabled. fault 0 1 x no the device is currently in fault mode. the faulted output(s) is (are) off. 0 x 1 fail- safe 1 0 1 yes watchdog has timed out and the device is in fail- safe mode. the outputs are as configured with the rfs resistor connected to fsi. rst and wake must be transitioned to logic [0] simultaneously to bring the device out of the fail- safe mode or momentarily tied the fsi terminal to ground. 1 1 1 1 1 0 x = don?t care. table 12. output state during fail-safe mode rfs (k ? ) high-side state 0 fail-safe mode disabled 6.0 both hs0 and hs1 off 15 hs0 on, hs1 off 30 both hs0 and hs1 on f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33984 motorola analog integrated circuit device data 22 fault mode the 33984 indicates the following faults as they occur by driving the fs terminal to [0]: ? overtemperature fault ? open load fault ? overcurrent fault (high and low) ? overvoltage and undervoltage fault the fs terminal will automatically return to [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. fault information is retained in the fault register and is available (and reset) via the so terminal during the first valid spi communication (refer to table 9 , page 20). overtemperature fault (non-latching) the 33984 device incorporates overtemperature detection and shutdown circuitry in each output structure. overtemperature detection is enabled when an output is in the on state. for the output, an overtemperature fault (otf) condition results in the faulted output tu rning off until the temperature falls below the t sd(hys) . this cycle will continue indefinitely until action is taken by the mcu to s hut off the output, or until the offending load is removed. when experiencing this fault, the otf fault bit will be set in the status register and cleared after either a valid spi read or a power reset of the device. overvoltage fault (non-latching) the 33984 shuts down the output during an overvoltage fault (ovf) condition on the v pwr terminal. the output remains in the off state until the overvoltage condition is removed. when experiencing this fault, the ovf fault bit is set in the bit od1 and cleared after either a valid spi read or a power reset of the device. the overvoltage protection and diagnostic can be disabled trough spi (bit ov_dis). undervoltage shutdown (latching or non-latching) the output latches off at so me battery voltage between 5.0 v and 6.0 v. as long as the v dd level stays within the normal specified range, the inte rnal logic states within the device will be sustained. this ensures that when the battery level then returns above 6.0 v, the device can be returned to the state that it was in prior to the low v pwr excursion. once the output latches off, the outputs must be turned off and on again to re-enable them. in the ca se in[1:0] = 0, this fault is non-latched. the undervoltage protection and diagnostic can be disabled through spi (bit uv_dis). open load fault (non-latching) the 33984 incorporates open load detection circuitry on each output. output open lo ad fault (olf) is detected and reported as a fault condition when that output is disabled (off). the open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. the olf f ault bit is set in the status register. if the open load fault is removed, the status register will be cleared after reading the register. the open load protection can be disabled trough spi (bit ol_dis). overcurrent fault (latching) the device has eight programmable overcurrent low detection levels (i ocl ) and two programmable overcurrent high detection levels (i och ) for maximum device protection. the two selectable, simultaneously active overcurrent detection levels, defined by i och and i ocl , are illustrated in figure 4 , page 13. the eight different overcurrent low detect levels (i ocl0 , i ocl1 , i ocl2 , i ocl3 , i ocl4 , i ocl5 , i ocl6 , and i ocl7 ) are likewise illustrated in figure 4 . if the load current level ever reaches the selected overcurrent low detect level and the overcurrent condition exceeds the programmed overcurrent time period (t ocx ), the device will latch the effected output off. if at any time the current reaches the selected i och level, then the device will immediately latch the fault and turn off the output, regardless of the selected t ocl driver. for both cases, the device output will stay off indefinitely until the device is commanded off and then on again. reverse battery the output survives the applicat ion of reverse voltage as low as -16 v. under these conditions, the output?s gates are enhanced to keep the junction temperature less than 150c. the on resistance of the output is fairly similar to that in the normal mode. no additional passive components are required. ground disconnect protection in the event the 33984 ground is disconnected from load ground, the device protects itself and safely turns off the output regardless the state of the output at the time of disconnection. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33984 23 package dimensions pna suffix 16-terminal pqfn non-leaded package case 1402-02 issue b m m 2.2 2.20 0.05 c 0.1 c 0.05 c seating plane 4 2.0 1.95 0.00 12 1 ( 10x 0.4) m 0.1 c m 0.05 c a b c a b 0.1 4.6 5.0 c 0.1 a b 9x 0.9 2x 1.075 6x 2.05 1.55 1.85 3.55 (2) 6x 0.8 0.4 2x 1.28 0.88 6 places 0.15 0.05 ( 10x 0.5) (0.5) 10.7 10.3 c 0.1 a b 11.2 10.8 ( 2x 0.75) 4x 1.45 1.05 c 0.1 a b 5.5 5.1 c 0.1 a b 2.25 1.75 ( 10x 0.25) 2.5 2.1 6x 1.1 0.6 2x 0.95 0.55 m 0.1 c m 0.05 c a b 10x 0.6 0.2 13 14 15 16 pin 1 index area 12 b c 0.1 2x 2x c 0.1 a 12 1 12 16 15 pin number ref. only detail g notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. the complete jedec designator for this 5. minimum metal gap should be 0.25mm. package is: hf-pqfp-n. 4. coplanarity applies to leads and corner leads. detail g view rotated 90? clockwise view m-m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution: p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information cent er, 3-20-1 minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre , 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. 852-26668334 technical information center: 1-800-521-6274 MC33984/d motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limit ation consequential or incidental damages. ?typical? parameters can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not c onvey any license under its patent rights nor the rights of oth ers. motorola products are not designed, intended, or authorized for use as components in system s intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other appl ication in which the failur e of the motorola product could create a situation where persona l injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and h old motorola and its officers, employees, subsidiaries, affiliate s, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal in jury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc . motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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